VHDL

Description

VHDL: Design, Synthesis, and Simulation is a textbook designed to meet the requirements of undergraduate students of electrical engineering (EE), computer science and engineering (CSE), information technology (IT), and electronics and communication engineering (ECE). This book would be useful for postgraduate students studying the related course while it would also serve as an invaluable reference for practising engineers.

The book begins with an introduction to the concepts of digital logic design and moves on to cover the fundamentals of VHDL. Modelling types such as dataflow, behavioural, structural, and mixed modelling are covered as separate chapters. Chapters on concurrent statements and sequential statements are covered next. The design aspect of the subject begins with the chapter on arithmetic logic unit (ALU) design, model simulation, delay modelling, followed by verification and testing. The synthesis of circuits at the register transfer level (RTL) is detailed next, followed by a chapter on placing and routing. Subsequently, comes a chapter on design examples addressing topics such as multiplier, divider, FIFO, and UART, where microcontroller is discussed in detail. The last chapter is dedicated to Verilog, yet another hardware description language with an introduction to its basic syntax, modelling, and design along with examples.

Loaded with plenty of programming examples and exercises, the book would be an ideal resource for students to gain mastery over the language.

Table of contents

1. Introduction to Digital Logic Design
2. Introduction to VHDL
3. Dataflow Modeling
4. Behavioral Modeling
5. Structural Modeling
6. Mixed Modeling
7. Concurrent Statements
8. Sequential Statements
9. Advanced VHDL
10. Arithmetic Logic Unit Design
11. Model Simulation
12. Delay Modeling
13. Verification and Testing
14. Synthesis
15. Place and Route
16. File I/O
17. Floating-point Arithmetic
18. Design with FPGA and CPLD
19. Memories and Buses
20. Design Examples
21. Introduction to Verilog